The CMX940 is a low-power high performance Fractional-N PLL with fully-integrated wideband VCO and programmable output divider, generating RF signals over a continuous frequency range of 49 MHz to 2040 MHz.
It has two level-controlled single-ended RF outputs to support Tx and Rx sub-systems. A highly-configurable near noiseless clock multiplier can be used to minimise close-in phase noise and mitigate integer and fractional boundary spurious. The chip configuration is controlled by an SPI-compatible C-BUS serial interface.
Available in a 7 x 7 mm LGA-48 package, the CMX940 reduces component count and PCB board area, requiring only external loop filter and clock reference to provide a complete and very compact RF synthesizer solution.
Low operating voltage and low power consumption make it the perfect choice for a wide variety of portable and battery powered wireless applications, including digital narrowband two-way radio equipment compliant with ETSI PMR co-existence standards applicable under the Radio Equipment Directive.
Devices are available through our distributors below:
||The PE0003 Evaluation Kit Interface Card is a global interface system for use with evaluation kits for CML’s new generation ICs, including FirmASIC™ based products. This greatly simplifies the approach to the evaluation and design-in process.||Link to: PE0003_Product_Page
PE0003 Driver – Windows should automatically load the correct driver when the PE0003 is connected via USB and powered on. If the driver fails to load then this can be downloaded from the PE0003 page above.
|The EV9400 Evaluation Kit is designed to assist in the evaluation and application development of the CMX940.
A GUI for the PE0003 that provides an automated visual design tool for the EV9400. The tool allows the user to interactively develop PLL settings for the EV9400 and export those settings or import settings from another source such as the Octave-based PLL Simulation tool. A spur avoidance algorithm allows a designer to rapidly develop a library of device settings for their project. Calibration values can be captured and re-written to allow rapid channel switching with extremely fast lock times for evaluation in TDMA settings. – Please register or login to download
EV9400 DWG. A higher resolution schematic for the evaluation kit EV9400, MOD state 2 – Please register or login to download
EV9400 BOM. Bill of materials for the evaluation kit EV9400 RevD, MOD state 2 – Please register or login to download
PCB Design Files. RevD – Please register or login to download
CMX940 PLL Simulation Tool. For calculating the phase noise and PLL settings in Octave. The PC GUI tool provides an interactive environment using the same method for deriving the PLL settings with spur avoidance. – Please register or login to download
Ev9400 Overlays. . A hi-resolution image set for the top and bottom layer component overlay of the EV9400 Rev D, Mod State 2. – Please register or login to download