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Features
Single Chip Full Duplex CVSD Codec
On-Chip Input and Output Filters
3- or 4-Bit Compand Algorithm
Force Idle and Powersave Facilities
Programmable Sampling Clocks
Separate Rx and Tx Paths
Fully Meets 'Mil-STD-188-113'
Simple Control
Robust Coding for Wireless Links
Single Chip Full Duplex CVSD Codec
On-Chip Input and Output Filters
3- or 4-Bit Compand Algorithm
Force Idle and Powersave Facilities
Programmable Sampling Clocks
Separate Rx and Tx Paths
Fully Meets 'Mil-STD-188-113'
Simple Control
Robust Coding for Wireless Links
Applications
Military Communications Field Exchange and Telephone Systems
Delta Multiplex, Switch and Phone
Voice Data
Military Communications Field Exchange and Telephone Systems
Delta Multiplex, Switch and Phone
Voice Data
Package Styles:
- MX629J - MX629LH - MX629P
Supply Requirement:
5.0V power supply
Description
The MX629 is an LSI circuit designed as a Continuously Variable Slope Delta Codec and is intended for use in military communications systems.
Designed to meet Mil-Std-188-113 with external components, the device is suitable for applications in military Delta Multiplexers, Switches and ‘Phones.
Encode input and decode output filters are incorporated on-chip. Sampling clock rates can be programmed to 16, 32 or 64 kbits/second from an internal clock generator or may be externally applied in the range 8 to 64 kbits/s.
Sampling clock frequencies are output for the synchronization of external circuits.
The encoder has an enable function for use in multiplexer applications. Encoder and Decoder forced idle facilities are provided, forcing a 10101010..... pattern in encode and a VDD/2 bias in decode.
The companding circuits may be operated with a pin-selected 3 or 4-bit algorithm.
The powersave facility puts the device into the standby mode thereby reducing current consumption when not operating.
A reference 1.024MHz oscillator uses an external clock pulse or Xtal input.
The MX629 is an LSI circuit designed as a Continuously Variable Slope Delta Codec and is intended for use in military communications systems.
Designed to meet Mil-Std-188-113 with external components, the device is suitable for applications in military Delta Multiplexers, Switches and ‘Phones.
Encode input and decode output filters are incorporated on-chip. Sampling clock rates can be programmed to 16, 32 or 64 kbits/second from an internal clock generator or may be externally applied in the range 8 to 64 kbits/s.
Sampling clock frequencies are output for the synchronization of external circuits.
The encoder has an enable function for use in multiplexer applications. Encoder and Decoder forced idle facilities are provided, forcing a 10101010..... pattern in encode and a VDD/2 bias in decode.
The companding circuits may be operated with a pin-selected 3 or 4-bit algorithm.
The powersave facility puts the device into the standby mode thereby reducing current consumption when not operating.
A reference 1.024MHz oscillator uses an external clock pulse or Xtal input.
