Integration of all AIS functions, including versatile synchronisation and timing and control facilities are available on this single compact IC. Control and interfacing, including upgraded ‘data-streaming’, are via the CML C-BUS serial interface, with a host-controlled expansion port for the addition of other CML (or other) ICs.
A third, parallel (Rx) decode path, accommodates the additional DSC (FSK) signalling from an external
modem for Class A AIS applications.
With its high integration on-chip of AIS-specific functions and wide-ranging data-signal processing
capabilities, the CMX910 reduces the final-product board-area requirement and component count whilst
drastically reducing the host µC load by minimizing the software generation effort; all with a
view to an accelerated time-to-market.
The provision of the C-BUS expansion port, an RF device enabling port and a number of auxiliary ADCs and DACs,
simplifies the system hardware implementation, further reducing the overall equipment cost and size.
The use of a single multi-function product offers significant reduction in power requirements.
Requiring a supply input in the range 3.0 to 3.6 volts, the CMX910 is available in both compact
64-pin LQFP and VQFN packages.
Enhancement
To further enhance the CMX910, its Special Command Interface (see section 5.12 of the latest CMX910 data sheet)
can be used to reconfigure the CMX910's functionality to fully implement and improve its CS-TDMA reception capability.
For further information, please see the CMX910 Initialisation Procedure information available from the
CMX910 Technical Portal area.
Block Diagram
