4FSK RD-LAP Packet Data Modem
Half Duplex, 4.8kb/s to 19.2kb/s Operation
Full Data Packet Framing
Flexible Operation Modes Host Processor Interface
The FX929B is a CMOS integrated circuit that contains all of the baseband signal processing and Medium.
Access Control (MAC) protocol functions required for a high performance 4FSK Wireless Packet Data Modem.
It interfaces with the modem host processor and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data over the wireless link.
The FX929B assembles application data received from the processor, adds forward error correction (FEC) and error detection (CRC) information and interleaves the result for burst-error protection.
After adding symbol and frame sync code-words, it converts the packet into filtered 4-level analogue signals for modulating the radio transmitter.
In receive mode, the FX929B performs the reverse function using the analogue signals from the receiver discriminator.
After error correction and removal of the packet overhead, the recovered application data is supplied to the processor.
Any residual uncorrected errors in the data will be flagged. A readout of the SNR value during receipt of a packet is also provided.
The FX929B uses data block sizes and FEC/CRC algorithms compatible with the RD-LAP over-air standard.
The format used is suitable for other private applications which require the high-speed transfer of data over narrow-band wireless links.
The device is programmable to operate at most standard bit-rates from a wide choice of Xtal/clock frequencies.
Design Support Information
|FX919B and FX929B Fade management and 'A' version compatibility
||Fade management and 'A' version compatibility