CMX649 and DE6491 FAQ
Q. Whilst using the DE6491 Demo Kit, audio output quality sometimes deteriorates. Is there any advice that can be offered to alleviate this phenomenon?
A: The most common reason for an increase in noise and reduction in voice quality is the state of the onboard batteries.
The kits are designed to function with a 2.9 - 5.5 V power supply or with two alkaline AAA batteries. It is clear that whatever batteries are chosen, their voltage will drop over time and fall below the 2.9V minimum level; this will effect overall Bit Error Rate and consequently output voice quality and noise floor.
Q. I am interested in establishing a voice link between a CMX639 and CMX649. How do I configure the CMX649 for this application?
A: While the CMX649 can perform CVSD voice coding through its first order integration, the CMX649 is not signal compatible with the CMX639, and hybrid systems using both devices should not be attempted.
Q. What is the “burst” mode?
A. The CMX649 provides two means of data exchange for Tx data output and Rx data input: burst mode and non-burst mode.
The burst mode allows data to be exchanged with the CMX649 in eight-bit or sixteen-bit bytes, while the non-burst mode causes the CMX649 to process data (encode and decode) one bit at a time.
Bits 2-0 of the CODEC MODE CONTROL register ($70) determine whether the CMX649 operates in 8/16-bit burst mode or non-burst mode. All burst modes are eight-bit with the exception of “Linear PCM with buffered I/O” mode, which is a sixteen-bit scheme.
(Note: The that the lowest three bits of the sixteen-bit PCM output word should be ignored in “Linear PCM with buffered I/O” mode.)
In general, burst mode operation relies primarily on three timing signals:
SYNC pulse: applied to the STROBE pin, used to mark byte boundaries
BURST CLOCK: applied to the RX CLK pin, used to clock in/out individual data bits.
Bit Clock: derived internally for both Tx and Rx operation.
The “sync” pulse should be applied on the STROBE pin every eight or sixteen bit times, depending on the selected operating mode.
The TX CLK and RX CLK pins are automatically forced to become inputs during burst mode operation. The BURST CLOCK signal must be applied to the RX CLK pin during burst mode operation, regardless of whether encode or decode operation is performed.
Burst mode operation requires that the encode and decode bit clocks be internally derived from the XTAL/CLK input.
When sending data to the write only registers, RPLY will be taken low for the duration of the second byte transfer. This is an anomaly and should be ignored as it will not affect normal operation. If communicating with C-Bus via an SPI port, caution must be applied to make sure that a bus conflict does not occur. A low value resistor placed in series between MISO and RPLY should resolve the problem.