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Advanced Digital Radio Baseband Processor



  • Programmable Digital Tx and Rx Filters
  • High Performance Codecs
  • 2 x 16-Bit Sigma-Delta ADC
  • 2 x 14-Bit Sigma-Delta DAC
  • 6 x 10-Bit ADC
  • 4 x 10-Bit DAC
  • 14-Bit Linear Codec with Digital Filter
  • pi/4 DQPSK and Other Modulations
  • C-BUS and 3 x Fast Serial Bus Interfaces
  • Low Power Requirement
  • 100mW Speaker Amplifier
  • 16.5mW Earpiece Amplifier


  • Digital Radio Including TErrestrial Trunked RAdio (TETRA) Systems
  • RCR-39 Systems (Japan)
  • Digital Wireless Local Loop
  • SATCOM Terminals
  • Terrestrial Flight Telephone Systems
  • High Speed Wireless Data Modems
  • Mixed-Mode Analogue/Digital Radio Networks

Supply Requirement:

  • 2.5V Supply with 3.3V Tolerant I/O

The CMX981 Advanced Digital Radio Baseband Processor is a combination codec/processor that interfaces analogue and digital sections of a Digital Radio System and performs critical DSP-intensive functions.

The device supports many digital portable, mobile and base station system applications including TETRA, APCO25, RCR-39 (Japan) and is also sufficiently flexible for use in other demanding digital radio systems.

The CMX981 transmit path comprises all functions required to convert digital ‘symbol’ data into suitably filtered analogue I and Q signals for external up-conversion and transmission. This includes digital control of output amplitudes and offsets and fully programmable digital filters.

Default coefficients provide the root raised cosine (RRC) response required for TETRA.

The CMX981 receive path accepts differential analogue baseband I/Q signals, samples them and performs digital channel select filtering to simplify host processing and data extraction. Internal digital offset correction and the digital filters are fully programmable.

Default coefficients provide the RRC response required for TETRA.

Auxiliary DAC and ADC functions are included for the control and measurement of the radio system RF section. This may include AFC, AGC, RSSI, or part of the control system for a Cartesian loop.

The voice codec converts voice signals to and from digital form and can be configured to apply a digital voice filter per specification G.712.

The encode path accepts a differential analogue audio input signal, converts it to digital form and applies digital voice filtering to produce a processed digital stream.

The decode path accepts a digital stream written to the serial interface, applies digital voice filtering, converts the result to an analogue signal, and presents the signal at differential speaker or single-ended earphone analogue driver outputs.

This path also includes a sidetone addition and a ring-tone generator.

Block Diagram

CMX981: An Advanced Digital Radio Baseband Processor that is a combination codec/processor to interface analogue and digital sections of a Digital Radio System.

Design Support Information



Q. Can you suggest a method of implementing an AGC with the CMX980A or CMX981?

A. The following text illustrates one method of Automatic Gain Control or AGC, a method employed to ensure that the optimum received signal is used when receiving and decoding a signal.
A received signal level will be very much higher when the receiver is located adjacent to a base station than it would be situated 2 miles from a mobile unit.

Figure 1 is a simple illustration of one method of AGC (Automatic Gain Control).
The Figure 1 shows a low noise, linear VGA (Variable Gain Amplifier) is used in the IF of the radio section. This is driven by one of the onboard CMX980A DACs and updated regularly when receiving.
The VGA will be used for coarse level adjustment, prior to down converting too Baseband.
Its main purpose is to ensure the CMX980A ADC’s are not saturated and the signal distorted.
Internally the Gain and Offset block will also be used to offer smaller, higher rate adjustments to incoming signal level. This unit’s purpose is to fine-tune the incoming signal to make full use of the IQ decoder.
The received IQ amplitude data is sent to the local Microcontroller/DSP that performs the final decoding and for calculating the required “on-the-fly” adjustments to the two-stage AGC.

Figure 1

Figure 1, a block diagram of the CMX980A receiver’s path and AGC implementation.

Figure 2, represents the received constellation diagram as perceived by the controlling Microcontroller/DSP. For decoding, the 8 constellation points that make up a good Pi/4DQPSK signal are used to calculate the received 3bit symbols by location in the diagram.
The purpose of AGC is to ensure that at all times the 8 IQ points remain stable and in a similar position no matter where the radio receiver is located or the amplitude of the incoming signal. If the signal amplitude increases in strength the 8 points will move outwards perpendicular to the centre position, if the signal decreases the points move towards the centre. See Figure 2, blue constellation point.

To try an maintain a reliable decode of the IQ points, thresholds can be set up that react to the position of the IQ points.
In figure 2 the minimum threshold is marked in red and the maximum in green. In this document they will be referred to as min_limit and max limit.

Figure 2

Figure 2, I and Q constellation diagram
By taking a period T (where T > Symbol rate) the samples that make up the 8 IQ points are averaged. If the mean is higher than max_limit then the receive gain will be reduced. If the mean is lower than min_limit then the receive gain is increased.

It is important to use average (mean) values to ensure that the gain feedback loop bandwidth is high and that the incoming signal is not artificially modulated.
Whatever period T is chosen it will be ultimately limited by the refresh rate of the CMX980A DAC and gain blocks.

It is intended that the VGA be used as a gross gain element that is updated periodically when there is consistent movement in received signal amplitude.

The CMX980A gain and offset block is intended for smaller but more frequent gain adjustments.

This method can also be used to update the offset block in the CMX980A by ensuring that the sum of the IQ points are equal to zero.

It is important to note that the decoder algorithm being used must be aware of the adjustments being made to the received signal and compensate for it when calculating symbol values and consequently decoding data.

In summary:
IQ signal is greater than max_limit (mean value over period T1) then reduce CMX980A gain block value.

If T1 remains positive for period T2 then reduce VGA.

IQ signal less than min_limit (mean value over period T1) then increase CMX980A gain block value.

If T1 remains negative for period T2 then increase VGA.

Additional hysteresis should also be included to decrease ripple and improve SINAD.

Q. I see that I and Q methods of generating and receiving baseband signals for wireless data devices is popular with CML, can you direct me to sources of I/Q hardware; for example I/Q mixers?

A. CML has a range of devices supporting I/Q architectures including the CMX991 (I/Q transceiver), CMX992( I/Q receiver), CMX993 (I/Q modulator) and CMX998 (Cartesian Loop modulator).

There are also many manufacturers of semiconductor solutions for I and Q radios, a comprehensive list would be difficult to maintain, however the first companies you should consider visiting are as follows:

Functions Manufacturer Link
IF AGC amplifiers, I/Q mixers, PLL’s, modulators and demodulators
Analog Devices

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