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Digital-radio Baseband Processor


This product is not preferred for new designs

Preferred product list:

  • CMX983 - AFE including two RF fractional-N synthesisers

Design Support Information



Q. Can you suggest a method of implementing an AGC with the CMX980A or CMX981?

A. The following text illustrates one method of Automatic Gain Control or AGC, a method employed to ensure that the optimum received signal is used when receiving and decoding a signal. A received signal level will be very much higher when the receiver is located adjacent to a base station than it would be situated 2 miles from a mobile unit.

Figure 1 is a simple illustration of one method of AGC (Automatic Gain Control).
The Figure 1 shows a low noise, linear VGA (Variable Gain Amplifier) is used in the IF of the radio section. This is driven by one of the onboard CMX980A DAC’s and updated regularly when receiving.
The VGA will be used for coarse level adjustment, prior to down converting too Baseband.
Its main purpose is to ensure the CMX980A ADC’s are not saturated and the signal distorted.
Internally the Gain and Offset block will also be used to offer smaller, higher rate adjustments to incoming signal level.
This unit’s purpose is to fine-tune the incoming signal to make full use of the IQ decoder.

The received IQ amplitude data is sent to the local Microcontroller/DSP that performs the final decoding and for calculating the required “on-the-fly” adjustments to the two-stage AGC.

Figure 1

Figure 1, a block diagram of the CMX980A receiver’s path and AGC implementation.

Figure 2, represents the received constellation diagram as perceived by the controlling Microcontroller/DSP. For decoding, the 8 constellation points that make up a good Pi/4DQPSK signal are used to calculate the received 3bit symbols by location in the diagram.
The purpose of AGC is to ensure that at all times the 8 IQ points remain stable and in a similar position no matter where the radio receiver is located or the amplitude of the incoming signal.
If the signal amplitude increases in strength the 8 points will move outwards perpendicular to the centre position, if the signal decreases the points move towards the centre. See Figure 2, blue constellation point.
To try an maintain a reliable decode of the IQ points, thresholds can be set up that react to the position of the IQ points. In figure 2 the minimum threshold is marked in red and the maximum in green. In this document they will be referred to as min_limit and max limit.

Figure 2

Figure 2 - I and Q constellation diagram

By taking a period T (where T > Symbol rate) the samples that make up the 8 IQ points are averaged. If the mean is higher than max_limit then the receive gain will be reduced. If the mean is lower than min_limit then the receive gain is increased.
It is important to use average (mean) values to ensure that the gain feedback loop bandwidth is high and that the incoming signal is not artificially modulated. Whatever period T is chosen it will be ultimately limited by the refresh rate of the CMX980A DAC and gain blocks.
It is intended that the VGA be used as a gross gain element that is updated periodically when there is consistent movement in received signal amplitude.
The CMX980A gain and offset block is intended for smaller but more frequent gain adjustments.
This method can also be used to update the offset block in the CMX980A by ensuring that the sum of the IQ points are equal to zero.
It is important to note that the decoder algorithm being used must be aware of the adjustments being made to the received signal and compensate for it when calculating symbol values and consequently decoding data.

In Summary:
IQ signal is greater than max_limit (mean value over period T1) then reduce CMX980A gain block value.
If T1 remains positive for period T2 then reduce VGA.
IQ signal less than min_limit (mean value over period T1) then increase CMX980A gain block value.
If T1 remains negative for period T2 then increase VGA.
Additional hysteresis should also be included to decrease ripple and improve SINAD.
Note: T2 >> T1

Q. What is the difference between the various direct write modes of the CMX980A?

Q. How do I write to constellation points other than those of Pi/4 DQPSK?

Q. Can I use a different modulation method on the CMX980A Baseband Processor.

A. Direct writes can be done at a number of points and it is locating the correct registers that gives the relevant data.

1. TxData:
Data write with symbol modulator not bypassed.

This format uses the 8 least significant bits to write 4 symbols to the symbol modulator which generates a stream of 3 bit values for the lookup-table. The look-up table then outputs the absolute I and Q values that represent the constellation point. This format is used to write symbol data directly on Pi/4 DQPSK systems but allowing the user to ignore the calculation of the I and Q values and the encoding method.

Data write with symbol modulator bypassed.

This format uses the last 3 significant bits to write directly to the look-up table, bypassing the symbol modulator. This allows the user to directly map one of the pi/4 DQPSK points without having to calculate the associated I and Q values.

This permits writing data directly to the Tx Data path at the sigma-delta DAC. This is raw data and is 14 bits in length. Two subsequent writes are required and the writes must be at least as fast as the sample rate. A user would use this format to generate an alternative modulation scheme FFSK (for example) in a system where other modulation schemes AND Pi/4 DQPSK are required. The method bypasses much of the CMX980A processing path and so a good deal of signal pre-processing would be required. The 12-bit value is not signed and corresponds directly to one of 4096 discrete steps. Both the I and the Q channel must be written.

4. DirectWrite79tapI and DirectWrite79tapQ:

This permits data writes at the symbol rate and writes directly to the 79-tap FIR filter. A 12-bit value can be written in one write cycle where the most significant bit (of the 12 bits) is the sign bit. This method allows the designer to use the signal path filtering which can be written with the designer own co-efficients. This permits the user to generate an alternative modulation scheme that uses different constellation points from Pi/4 DQPSK.

Q How do I adjust the Tx symbol clock on the CMX980A?

A. The CMX980A provides a mechanism by which the Tx symbol clock phase can be adjusted to a resolution of 1/8th of a symbol.

The adjustment to the Tx symbol clock is made by writing to the SymClkPhase ( $0x24 ) register. Adjustments to the symbol clock phase must be made before a transmit burst is started. To understand this mechanism it must be understood that the internal CMX980A transmit symbol clock is running continuously. It can be monitored at IRQN by setting the n_SymbolClkEn_Mask bit3 of the TxErrStatMask ( $0x0F ) register.

The adjust mechanism is effectively a two state finite state machine (fsm). On reset it is placed in the IDLE state.

When the symbol adjust register is written to with the lsb ( bit 0) HI it moves the fsm to the READY state. A second write to the register will program the adjustment (bit1 sets the amount of shift (1/8 or 1/4 of a symbol period) and bit2 the required direction) into the CMX980A which will make the adjustment at the next internal symbol clock. For the second write, if bit0 is LO the fsm will go to the IDLE state, but if bit0 is HI the fsm will remain READY and a third write could be used to increase the adjustment in symbol clock phase.

At every symbol clock any programmed adjustments are made and the fsm returns to IDLE. The state of the fsm can be determined at any time by reading the SymClkPhase register and checking bit0, HI is READY, LO is IDLE.

This mechanism was designed for synchronous operation. i.e. monitor the symbol clock at IRQN, make writes to SymClkPhase register between two clock pulses at IRQN.

1/ Program +1/8th symbol adjustment.

// called by Interrupt Service Routine when symbol clock pulse occurs>

// at IRQN

WR980(SYMCLKPHASE,b"001") // fsm to READY.

WR980(SYMCLKPHASE,b"010") // load +1/8th symbol, fsm to IDLE.

2/ Program -3/8th symbol adjustment.

// called by Interrupt Service Routine when symbol clock pulse occurs.

// at IRQN

WR980(SYMCLKPHASE,b’001’) // fsm to READY.

WR980(SYMCLKPHASE,b"101") // load -1/4 adjust, fsm still ready

WR980(SYMCLKPHASE,b’000’) // load -1/8 adjust, fsm to IDLE.

1st Write ‘arms’ the phase adjustment

2nd Write loads and ‘executes’ the phase adjustment


Relative phase adjustment of a symbol using the SymClkPhase Register

If a customer does not wish to monitor IRQN for transmit symbol clock it is possible to time an adjustment by polling bit0 of the SymClkPhase register. i.e. make 1 write to put fsm in READY state but not program an adjustment. Then, read SymClkPhase register until bit0 is LO i.e. a symbol clock has occured and fsm is IDLE.

3/ Program +1/4 symbol by polling.

WR980(SYMCLKPHASE,b’001’) // fsm to READY.

Loop {

RD980(SYMCLKPHASE) // poll the SymClkPhase register

}until(bit0=LO) // until bit0 is LO, ie fsm IDLE.

WR980(SYMCLKPHASE,b’001’) // fsm to READY.

WR980(SYMCLKPHASE,b’110’) // load +1/4 symbol, fsm to IDLE.

Q. Should the 1.5nF capacitor on the Rx inputs be NP0 / C0G types or are X7R and similar parts suitable?

A. NPO / COG capacitors are usually found in RF circuits where the first point at which self-resonance occurs is very high. The capacitors will be coupling baseband signals only and therefore X7R and similar general purpose types will be suitable.

Q. Will any activity on the serial interface with the supply removed damage the CMX980A?

A. Yes, removing the supply will result in internal voltages falling to 0V but external pins, connected to active circuits, could see amplitudes approaching full supply level.

The data sheet gives the maximum permissible voltage on any pin to VSS as any of; VDD, VCC1 / 2 / 3 or VDD1; + 0.3V. Therefore, when not powered, this maximum voltage that can be applied to any pin is 0.3V.

Q. Is it possible to independently powersave either the digital or the analogue parts of the CMX980A?

A. There is no level translation or current limiting circuits within the CMX980A that will allow a difference in supply voltage between the analogue and digital sections. Both supplies must be equal in amplitude to avoid damage to the CMX980A.

Q. I need a filter response other than root-raised cosine (RRC), but I see that the CMX980A has root-raised cosine filter shaping as its default filter response.
Can the CMX980A perform any other type of filter shaping?

A. Yes. The 63-tap FIR filter in the Tx path and the second 63-tap FIR filter in the Rx path can be configured with coefficients to perform various filter responses. The coefficients required to accomplish a desired filter characteristic can be determined by the use of third-party coefficient calculation software.

Remember to scale the coefficients appropriately to prevent overflows. Also, when determining the filter characteristic to be used, be sure to consider the impact of your filter choice on the overall system performance. For example, a departure away from RRC filtering will allow the introduction of inter-symbol interference (ISI) into your system, and this must be accounted for to ensure acceptable BERs.
Consideration must also be given to the amount of filtering applied to the data stream; the more aggressive the filtering, the more spectrally efficient the transmission but the more ISI that will be introduced.

Q. 980 I do not want to use both the 79-tap and the 63-tap filters in the Tx path. Can I avoid one of them?

A. Yes. Writing a “unity coefficient” (see data bulletin for more information) to a single location in the filter coefficient registers will allow that filter to effectively be bypassed.
In the case of the 79-tap filter, this "unity coefficient" must be written to the center tap of the filter; otherwise, the symmetrical coefficients used by this filter will cause a second "unity coefficient" to be written to the register, resulting in the filter not being bypassed.

Q. I am using the CMX980A in a non-TETRA application. I am writing my own filter coefficients and I am writing my Tx data using the "direct Tx write to 79 tap filter" method.
I can see no output signals on the I and Q pins. What am I doing wrong?

A. It is likely that you have the "CoeffRamIoEn" bit set incorrectly.

When initializing the device for the "direct Tx write to 79 tap filter" method, the CoeffRamIoEn bit must be set to "1" in order to allow the default filter coefficients to be overwritten. This must be done prior to enabling the Tx path.
However, once the filter coefficients have been written as desired, the CoeffRamIoEn must be cleared to "0" before the Tx path is enabled; otherwise no output data will be seen at the I and Q pins

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