top menu
Site Menu Site Search

TWELP Vocoder



  • Half-duplex Operation
  • FEC Built-in
  • Noise Reduction
  • No External DSP or Codecs Required
  • Choice of Signal Input/Out Sources
  • No royalty/license fee
  • C-BUS Host Serial Interface
    • SPI-like with Register Addressing
    • Streaming Input/Output Registers, Low Host Latency
    • C-BUS/Host, PCM Codec, Analogue Audio Output
  • Auxiliary Functions
    • GPIOs
    • Analogue Input/Output Multiplexer
  • Low Power 3.3V Operation with Powersave Functions
  • Small 64-pin VQFN and 64-LQFP (L9) Packages


  • Digital Radio Systems
  • Personal Area Networks
  • Secure Digital Voice Comms
  • Wireless PBX
  • VoIP Applications
  • Digital Software Defined Radio (SDR)

Supply Requirement:

  • 3.0 to 3.6 V

The CMX7262 Professional Radio Vocoder IC is a device supporting Tri-Wave Excited Linear Prediction (TWELP) vocoder in a single chip.

TWELP is the latest state-of-the-art vocoder technology providing the highest quality natural sounding voice and good reproduction of non-voiced signals such as: police, fire and ambulance sirens.

TWELP is also extremely tolerant to acoustic noise and includes an advanced noise reduction system to suppress background noise and includes a decoder side noise gate

The robust FEC algorithm acts on individual vocoder frames for minimum latency and provides optimal performance mitigating bit errors inherent over narrowband radio channels. Modem soft decision bits are also supported to further maximise performance.

Input and output signals may be passed through the C-BUS interface or the on-chip analogue-to-digital and digital-to-analogue converters (ADC/DAC).

The device utilises CML’s proprietary FirmASIC component technology. On-chip sub-systems are configured by a Function Image data file that is uploaded during device initialisation and that defines the device's function and feature set.

The Function Image can be loaded automatically from a host µC over the C-BUS serial interface or from an external memory device. The device's functions and features can be enhanced by subsequent Function Image releases, facilitating in-the-field upgrades.

The CMX7262 operates from a 3.0V to 3.6V supply and includes selectable power saving modes. It is available in a 64-VQFN (Q1) and 64-LQFP (L9) packages.

Block Diagram

CMX7262 Block Diagram

Design Support Information



Q.  Should pull-up or pull-down resistors be connected to CMX7262 device GPIO pins (GPIOA, GPIOB, GPIOC, and GPIOD)?

A.  The CMX7262 features flexible GPIO pins that can be independently configured via C-BUS serial interface commands to operate in one of the following modes: CMOS digital output, CMOS digital input or CMOS digital input with bus hold. Bus hold automatically engages a 75kohm internal pull-up or pull-down resistor that reinforces the current logic state of the input signal. As is normally the case, the state of a CMOS digital input will be indeterminate and may increase device supply current when the input’s voltage is not at valid ‘0’ or ‘1’, i.e. when the node voltage is “floating.”

When the CMX7262 is RESET (by asserting its RESETN pin, issuing a C-BUS General RESET or by triggering an internal power on reset) all its GPIO pins are immediately placed in CMOS digital input mode. Any GPIO pins not being pulled either up or down by an external load will be floating. Once a Function Image™ is loaded into the device then all its GPIO pins are placed in CMOS digital input with bus hold.

If user circuits require one or more GPIO pins to be held at a deterministic ’0’ or ‘1’, i.e. not floating after RESET and before the Function Image™ is loaded then that circuit should connect external pull-up or pull-down circuits to such pins.

View our news as RSS Visit our twitter feed Visit our Youtube channel Visit our LinkinIn page Visit our facebook page
Web design by S-Digital
Copyright © 2014 CML Microsystems Plc