NAVIGATION
ASIC Design Flow and Development
The starting point for a CML Custom Design is the full understanding
of the customer's requirements, from which follows:
of the customer's requirements, from which follows:
The ASIC design is carried out using industry-standard design systems, based on Unix and Linux workstations with Cadence software tools.
- Generation of a Chip Specification
- Functional Modelling to Check System-level Design
- Synthesise Logic and Memory Blocks
- Use/Modify Existing Cell/Macro Functions
- Design New Cells/Blocks
- Analogue/Digital/Mixed-signal Simulation
- Full custom Layout and Verification of New/Modified Cells/Blocks
- Auto Place and Route Standard Cells
- Auto Place and Route Top-level Blocks
- Extraction/Back Annotation of Parasitics and Re-simulation
- Chip-level LVS/DRC
Design Systems
- Virtuoso:
- Schematic Editor
- Spectre Simulator
- Spectre RF Simulator
- Multimode Simulator
- Incisive Digital Verification
- Encounter Place and Route
- Encounter RTL Compiler
- Assura DRC/LVS
Additional Tools
- System Vue - for system level modelling of analogue and mixed-signal circuits
- Switcap - auto generation of capacitor arrays for SC filters
- Hercules DRC/LVI
ASIC Development Phases
The development of an ASIC by CML encompasses all aspects of a design, from 'Concept to Devices'.
Timescales
The timescale for the development phase is directly dependant on the complexity
of the ASIC and can vary from as little as a few weeks to several months.
- Generation of a Chip Specification
- Chip Design
- Customer Reviews
- Chip Layout and Verification
- Customer Sign-off Review
- Fabrication
- Engineering Wafer Run
- Multi-project Wafer (MPW) Run
- Manufacture Samples/Prototypes
- Customer Evaluation and Approval
- Production-test Hardware and Program Development
- Production Manufacture
- Product Shipments