// EV6180 Decode DTMF using Test Pattern // 2400bps, 1200bps FEC, 60ms packets // //Configuration R2 40 // clear IRQ from powerup W1 01 // General Reset // wait for IRQ, check for RDY and ACK bit W3 1D 0005 // W2 09 03 // POWERSAVE: enable codec & bias W2 07 37 // VCFG: DTMF Format 1, HDD, FEC, 2400bps, 60ms packets // wait for IRQ, check for RDY and ACK bit // wait for 100ms for Vbias to stabilize W2 05 8F // AIG: mic amp=20dB, Input gain=22.5dB W2 06 07 // AOG: earpiece gain=0dB, Output gain=0dB W3 1E 809E // VDWHLWM: High watermark=158 samples=19.75ms // wait for IRQ, check for RDY bit W3 1E 0048 // VDWHLWM: Low watermark=72 samples=9ms // wait for IRQ, check for RDY bit //Configuration complete, Setup decoder for DTMF Mode 1, Format 1 W3 11 0071 // VCTRL: DDTMFG, DDTMFD, DVDW, enable decoder // wait for IRQ, check for RDY and ACK bit W3 1F 0100 // IRQENAB: VDW //Write 1st DTMF Frame to DECFRAME W2 10 5c W2 10 84 W2 10 00 W2 10 c6 W2 10 00 W2 10 31 W2 10 a1 W2 10 80 W2 10 00 W2 10 19 W2 10 00 W2 10 49 W2 10 0c W2 10 84 W2 10 04 W2 10 20 W2 10 59 W2 10 b5 W2 10 81 W2 10 a2 W2 10 00 W2 10 40 W2 10 a0 W2 10 40 W2 10 44 W2 10 8d W2 10 45 //Write 2nd DTMF frame R2 40 //read Status register to clear IRQ W2 10 5c W2 10 84 W2 10 00 W2 10 c6 W2 10 00 W2 10 31 W2 10 a1 W2 10 80 W2 10 00 W2 10 19 W2 10 00 W2 10 49 W2 10 0c W2 10 84 W2 10 04 W2 10 20 W2 10 59 W2 10 b5 W2 10 81 W2 10 a2 W2 10 00 W2 10 40 W2 10 a0 W2 10 40 W2 10 44 W2 10 8d W2 10 45 //Write 3rd DTMF frame R2 40 //read Status register to clear IRQ W2 10 5c W2 10 84 W2 10 00 W2 10 c6 W2 10 00 W2 10 31 W2 10 a1 W2 10 80 W2 10 00 W2 10 19 W2 10 00 W2 10 49 W2 10 0c W2 10 84 W2 10 04 W2 10 20 W2 10 59 W2 10 b5 W2 10 81 W2 10 a2 W2 10 00 W2 10 40 W2 10 a0 W2 10 40 W2 10 44 W2 10 8d W2 10 45 //Write 4th DTMF frame R2 40 //read Status register to clear IRQ W2 10 5c W2 10 84 W2 10 00 W2 10 c6 W2 10 00 W2 10 31 W2 10 a1 W2 10 80 W2 10 00 W2 10 19 W2 10 00 W2 10 49 W2 10 0c W2 10 84 W2 10 04 W2 10 20 W2 10 59 W2 10 b5 W2 10 81 W2 10 a2 W2 10 00 W2 10 40 W2 10 a0 W2 10 40 W2 10 44 W2 10 8d W2 10 45 //Write 5th DTMF frame R2 40 //read Status register to clear IRQ W2 10 5c W2 10 84 W2 10 00 W2 10 c6 W2 10 00 W2 10 31 W2 10 a1 W2 10 80 W2 10 00 W2 10 19 W2 10 00 W2 10 49 W2 10 0c W2 10 84 W2 10 04 W2 10 20 W2 10 59 W2 10 b5 W2 10 81 W2 10 a2 W2 10 00 W2 10 40 W2 10 a0 W2 10 40 W2 10 44 W2 10 8d W2 10 45 //Write 6th DTMF frame R2 40 //read Status register to clear IRQ W2 10 5c W2 10 84 W2 10 00 W2 10 c6 W2 10 00 W2 10 31 W2 10 a1 W2 10 80 W2 10 00 W2 10 19 W2 10 00 W2 10 49 W2 10 0c W2 10 84 W2 10 04 W2 10 20 W2 10 59 W2 10 b5 W2 10 81 W2 10 a2 W2 10 00 W2 10 40 W2 10 a0 W2 10 40 W2 10 44 W2 10 8d W2 10 45 //Write 7th DTMF frame R2 40 //read Status register to clear IRQ W2 10 5c W2 10 84 W2 10 00 W2 10 c6 W2 10 00 W2 10 31 W2 10 a1 W2 10 80 W2 10 00 W2 10 19 W2 10 00 W2 10 49 W2 10 0c W2 10 84 W2 10 04 W2 10 20 W2 10 59 W2 10 b5 W2 10 81 W2 10 a2 W2 10 00 W2 10 40 W2 10 a0 W2 10 40 W2 10 44 W2 10 8d W2 10 45 //Write 8th DTMF frame R2 40 //read Status register to clear IRQ W2 10 5c W2 10 84 W2 10 00 W2 10 c6 W2 10 00 W2 10 31 W2 10 a1 W2 10 80 W2 10 00 W2 10 19 W2 10 00 W2 10 49 W2 10 0c W2 10 84 W2 10 04 W2 10 20 W2 10 59 W2 10 b5 W2 10 81 W2 10 a2 W2 10 00 W2 10 40 W2 10 a0 W2 10 40 W2 10 44 W2 10 8d W2 10 45 //Write 9th DTMF frame R2 40 //read Status register to clear IRQ W2 10 5c W2 10 84 W2 10 00 W2 10 c6 W2 10 00 W2 10 31 W2 10 a1 W2 10 80 W2 10 00 W2 10 19 W2 10 00 W2 10 49 W2 10 0c W2 10 84 W2 10 04 W2 10 20 W2 10 59 W2 10 b5 W2 10 81 W2 10 a2 W2 10 00 W2 10 40 W2 10 a0 W2 10 40 W2 10 44 W2 10 8d W2 10 45 //Write 10th DTMF frame R2 40 //read Status register to clear IRQ W2 10 5c W2 10 84 W2 10 00 W2 10 c6 W2 10 00 W2 10 31 W2 10 a1 W2 10 80 W2 10 00 W2 10 19 W2 10 00 W2 10 49 W2 10 0c W2 10 84 W2 10 04 W2 10 20 W2 10 59 W2 10 b5 W2 10 81 W2 10 a2 W2 10 00 W2 10 40 W2 10 a0 W2 10 40 W2 10 44 W2 10 8d W2 10 45 w1 01